1. Field of Invention
The present invention relates generally to semiconductor integrated circuits and methods of fabricating such circuits. More specifically, it relates to semiconductor integrated circuits with an insulation structure having an a reduced permittivity incorporated therein.
2. Description of the Prior Art
As integrated circuits are scaled to meet the need for both higher performance levels and more complex integrated circuit solutions, the result is increased circuit density. One scaling method used is shrinking a circuit""s horizontal geometries, thus reducing the spacing between features. As features such as adjacent conductive paths are brought closer to one another, capacitive coupling between the paths can become a barrier to the scaling process.
Adjacent conductive paths can be viewed as a parallel plates of a capacitor and the insulating material between them as the capacitor""s dielectric. As it is known, capacitance is a function of the permittivity of the insulator (∈i) divided by the thickness of the insulator (xi).
xe2x80x83Cxe2x88x9d∈i/Xi
Thus capacitance increases between conductive paths, for any given dielectric material, as they are brought closer together by, for example, a scaling process. This increase in capacitance results in an increase in the RC time constant which, as it is known, causes a decrease in circuit speed. Additionally, increases in capacitance between adjacent conductive paths also result in increases in inductive noise or cross-talk between the adjacent conductors.
As the above mentioned equation indicates, when the spacing between conductors decreases the capacitance will increase unless the permittivity of the dielectric is lowered. However, lower permittivity is difficult to achieve due to the limited number of materials suitable for semiconductor processing. The most common dielectric material used is silicon dioxide with ∈i=3.9 Faradays/centimeter (F/cm). Other common dielectrics such as silicon nitride have a higher permittivity and therefore are not useful for reducing the permittivity of the dielectric.
On the other hand, vacuum has a permittivity of 1.0 F/cm and air a slightly higher 1.001 F/cm. Thus isolating adjacent conductive paths with vacuum, air or with a hybrid structure including a substantial portion of vacuum or air would be a solution. In addition, for any solution that results in a lower permittivity to have broad applicability it would also be required to be structurally sound and readily integrated into a standard semiconductor process. While several proposals for isolating adjacent conductive paths with vacuum, air or a hybrid material have been made, none meets the aforementioned requirements.
An early effort at a solution is seen in U.S. Pat. No. 3,890,636 entitled xe2x80x9cMULTILAYER WIRING STRUCTURE OF INTEGRATED CIRCUIT AND METHOD OF PRODUCING SAMExe2x80x9d issued to Harada et al. on Jun. 17, 1975 and assigned to Hitachi, Ltd. of Japan. Harada et al. teach a method that requires the formation of metal stanchions between each of the multiple layers of metal to isolate adjacent conductors. Thus the formation of this stanchion requires additional metal deposition, patterning and etching steps to form the stanchions. For a dual layer metal system, three metal depositions and three photolithograhic steps are required rather than two depositions and two patterning steps. In addition, all conductive paths are free standing with no additional supporting structures to provide for strength. Therefore, Harada et al. teaches that thicker and wider conductive paths are required to provide this strength. As it can be seen, the method of Harada et al. requires extra, costly processing steps and wider conductors that are adverse to sizing.
In U.S. Pat. No. 4,933,743, entitled xe2x80x9cHIGH PERFORMANCE INTERCONNECT SYSTEM FOR AN INTEGRATED CIRCUITxe2x80x9d issued to Thomas et al. on Jun. 12, 1990 and assigned to Fairchild Semiconductor Corp., a free standing structure is also taught. While Thomas et al. teach enclosing each conductor in a dielectric layer, that layer is primarily proposed to allow the open structure to be back-filled with a metallic material. Additionally, the dielectric layer surrounding the conductors adds little or no strength as it is supported by the metal rather than providing such support. Thus the structure of Thomas et al. does not provide the sound structure required unless additional costly processing is used, such as backfilling with a metallic material.
U.S. Pat. No. 5,119,164 entitled xe2x80x9cAVOIDING SPIN-ON-GLASS CRACKING IN HIGH ASPECT RATIO CAVITIESxe2x80x9d and issued to Sliwa Jr. et al. on Jun. 2, 1992, is directed to avoiding cracks in a spin-on glass (SOG) used as an insulating layer. The method teaches the deposition of a tungsten (W) layer as a peripheral coating for conductive metal stripes. After a spin-on glass is applied, the W is uncovered by, for example, etching back the spin-on layer. Subsequently the W is removed to form a void adjacent the metal stripe. Upon hard curing of the glass, this void increases in size due to densification of the SOG. While a void is formed, this method requires the deposition of an W layer and its subsequent removal. In addition, the void formed is unpredictable in its size and is easily filled in a multilayer device structure.
U.S. Pat. No. 5,310,700 entitled xe2x80x9cCONDUCTOR CAPACITANCE REDUCTION IN INTEGRATED CIRCUITSxe2x80x9d was issued to Chuen-der Lien et al. on May 10, 1994 and assigned to the same assignee of the present application, Integrated Device Technology, Inc. Lien et al. disclose a method for reducing the capacitance between a first and a second conductor on a semiconductor substrate. This patent is incorporated by reference herein. Lien et al. teach the formation of a cavity at an approximate midpoint between conductive stripes due to the effect of protrusions, formed at the top of the conductive stripes, upon the filling of the space between with an insulating material such as chemical vapor (CVD) deposited silicon oxide. While the method of Lien et al. is effective, it is both process and design layout dependent and requires forming an air gap independently for each layer.
U.S. Pat. No. 5,407,860 entitled xe2x80x9cMETHOD OF FORMING AIR GAP DIELECTRIC SPACERS BETWEEN SEMICONDUCTOR LEADSxe2x80x9d was issued to Stoltz et al. on Apr. 18, 1995. Stoltz et al. is directed to forming an air gap through the deposition of a non-wetting material, such as Teflon, as a thin layer overlying adjacent metal stripes. Stoltz et al. teach that upon deposition of an insulating material, the surface of the non-wetting material will not be wetted by the insulating material. In this manner, voids are formed. However, Stoltz et al. require a Teflon deposition process that is non-standard and thus difficult to incorporate into a semiconductor process flow. Additionally, the effect of the non-wetting surface is layout dependent making the size of the air gaps, if any, unpredictable.
Another method is taught in U.S. Pat. No. 5,461,003 entitled xe2x80x9cMULTILEVEL INTERCONNECT STRUCTURE WITH AIR GAPS FORMED BETWEEN METAL LEADSxe2x80x9d issued to Robert H. Haverman on Oct. 24, 1995. Haverman teaches the etching of a disposable dielectric layer through a porous, overlying layer. A silica-based xerogel with a porosity range of between 10-50% is taught by Haverman to be an appropriate porous layer. As it is known, the deposition of such a porous layer is not a standard semiconductor process and the porosity is a function of the removal of the dispersion medium. Thus such a process is difficult to reproducibly perform and integrate with other standard semiconductor process steps. Additionally, as this is a porous layer, additional, non-porous material must be employed to provide xe2x80x9cimproved structural support and thermal conductivity, and passivat[ion of] the porous dielectric layerxe2x80x9d (col. 6, ln. 12-13).
Japanese Pat. No. 1-189939A entitled xe2x80x9cSEMICONDUCTOR INTEGRATED CIRCUITxe2x80x9d and issued to Shigeru Murakami on Jul. 31, 1989, is directed to reducing capacitance between wiring on two different levels. Thus Murakami teaches forming an air gap between a lower wire 4 and an upper wire 7. Additionally this gap is formed by removing a photoresist layer using a release agent and anisotropic etching with CF4 gas. Therefore upper wire 7 must be formed over the photoresist layer. Murakami teaches forming upper wire 7 over an existing photoresist layer, which, as it is known, can lead to contamination of the wiring layer. Additionally, Murakami teaches etching with a fluorine containing gas which is a well known etchant of silicon oxide, thus potentially compromising insulating layers formed thereof.
Japanese Pat. No. 1-318248 entitled xe2x80x9cSEMICONDUCTOR DEVICE AND MANUFACTURE THEREOFxe2x80x9d issued to Takahiro Tsuchitani on Dec. 12, 1989, is directed to reducing the capacitance between an upper wiring level 5 and a lower wiring level 2 through the use of an air gap. Tsuchitani teaches that where an air isolation region 4 is beyond a certain dimension, support for upper wiring level 5 can be provided by forming struts 6. Thus Tsuchitani teaches forming an added structure requiring additional processing to provide for support of the upper wiring layer 5.
It can be seen that while a variety of methods of forming air gaps have been proposed, none provides for reduced capacitance between adjacent conductors on the same level, structural support for multilevel conductors, and easy integration into a semiconductor process flow.
Therefore a need exists for such a structure that provides for a reduced capacitance between adjacent conductive paths or a single level. A need also exists for a reduced-capacitance structure that can provide structural support for multilevel conductors. Finally, a need exists for such a solution to be easily integrated into an existing semiconductor process flow.
The present invention is directed to a method for forming an insulation structure for adjacent conductive paths in a semiconductor integrated circuit, wherein the structure has a permittivity substantially less than 3.9 F/cm. Additionally, the present invention is directed towards the specific structure formed by such a method.
The present invention provides adjacent conductive paths having substantially all of their sidewalls covered with an insulating layer. Additionally, according to the present invention a disposable layer is formed between the insulating layer covered sidewalls and another insulating layer is formed overlying the disposable layer and the conductive paths to provide structural support for multilevel conductive paths.
In addition, the present invention provides a method for the removal of a disposable layer to form an embodiment of a basic structure having a permittivity of less than 3.9 F/cm. This basic structure can be repeated any number of times to generate a multilayer metal integrated circuit. Prior to each repeated structure, or a final passivation layer, an array of openings is provided to allow removal of the disposable layer at a future process step.
Thus a basic structure is shown that is alternatively a building block or a final structure. In addition a method for creating same is also shown.